According to miniaturization in a semiconductor manufacturing process, the number of MOSFETs which are integrated in a single LSI (LSI: Large Scale Integrated circuits) has increased, with an accompanied increase of leakage current. Especially in the mobile use, under the limited battery capacity, a system on a chip (SoC) of this family needs to satisfy a demand for a strict leakage current. According to Non-patent Document 1 cited below, the effective method in such a situation is cutting off a power supply to a standby IP, while maintaining a power supply to a necessary IP. Therefore, the fine grained power gating system which employs many power domains is needed, in order to realize a low power consumption LSI for a mobile SoC.
Patent Document 1 cited below describes an information processing device in which, in order to manage to balance a low standby current by power gating and a high-speed return from a standby mode by interruption, a first area comprises a central processing unit and a peripheral circuit module and a second area comprises an internal memory and a backup register, and current supply is controlled by a first power switch in the first area and current supply is controlled by a second power switch in the second area. When shifting to a standby mode, internal information is evacuated to the internal memory or the backup register, then the first power switch is set to an off state to stop current supply to the first area, and the second power switch is set to an off state to maintain the internal information evacuated to the second area.
Patent Document 2 cited below describes that, in order to reduce the leakage current of an SRAM circuit, a switch, a diode coupling MOS transistor, and a resistor are coupled in parallel between a source line to which a source electrode of a drive MOS transistor is coupled and the ground potential line. At the time of standby, the switch coupled between the source line and the ground potential line is controlled into an off state, and the potential of the source line is set to a level higher than the ground potential by the relation of the leakage current of the memory cell, the diode coupling MOS transistor, and the resistor; accordingly, the leakage current is reduced. A switch MOS transistor is coupled between the ground potential and the ground-potential-side power source line of the peripheral circuit of SRAM except a word driver. The switch MOS transistor is controlled into an off state by a control signal at the time of standby. Therefore, the potential of the ground-potential-side power source line of the peripheral circuit of SRAM rises, and the leakage current of the peripheral circuit at the time of standby is reduced.
Patent Document 3 cited below describes that a leakage current reduction circuit is coupled between a low potential terminal of a latch circuit or an SRAM cell comprising a CMOS, and a ground potential. The leakage current reduction circuit comprises an NMOS switching transistor, a control PMOS transistor, and a control NMOS transistor. A drain-to-source path of the NMOS switching transistor is coupled between the low potential terminal and the ground potential. A source, a gate, and a drain of the control PMOS transistor are coupled to a power supply voltage, a standby signal terminal, and a gate of the NMOS switching transistor, respectively. A drain, a gate, and a source of the control NMOS transistor are coupled to the low potential terminal, a gate of the NMOS switching transistor, and the standby signal terminal, respectively. At the time of operation of the circuit, in response to a low level signal of the standby signal terminal, the control PMOS transistor, the control NMOS transistor, and the NMOS switching transistor are set to an on state, an off state, and an on state, respectively, and the low potential terminal is coupled to the ground potential through a low impedance. Therefore, the latch circuit or SRAM cell comprising a CMOS performs a normal operation. At the time of standby, in response to a high level signal of the standby signal terminal, the control PMOS transistor and the control NMOS transistor are set to an off state and an on state, respectively. The NMOS switching transistor operates like an MOS diode with the leakage current of the latch circuit or the SRAM cell comprising a CMOS as a bias current, thereby keeping the potential of the low potential terminal to a constant potential higher than the ground potential. Accordingly, the leakage current at the time of standby is reduced.
Patent Document 4 cited below describes that, in order to manage to balance a static noise margin and a write-in margin even at a low power source voltage in a static type RAM, a voltage supplying circuit is coupled between a power supply voltage line and a memory cell power source line. At the time of writing, a high-level control signal is supplied to a gate of a P-channel MOSFET of the voltage supplying circuit, and the P-channel MOSFET is set to an off state; accordingly, a voltage of the memory cell power source line is reduced. Therefore, the static noise margin is reduced and the write-in margin is improved.
(Patent Document 1) Japanese Patent Laid-open No. 2005-011166.
(Patent Document 2) Japanese Patent Laid-open No. 2004-206745.
(Patent Document 3) Japanese Patent Laid-open No. 2007-150761.
(Patent Document 4) Japanese Patent Laid-open No. 2006-085786.
(Non-patent Document 1) Yusuke Kanno et al, “Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, No. 1, JANUARY 2007, PP. 74-83.